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19-0379; Rev 0; 3/95
155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector
_______________General Description
The MAX3270 is a complete Clock Recovery and Data Retiming IC for 155Mbps and 622Mbps SDH/SONET and ATM applications. The MAX3270 meets Bellcore and CCITT jitter tolerance specifications ensuring errorfree data recovery. Recovered clock and data are phase aligned using a fully integrated phase-locked loop (PLL). An output frequency monitor (FM) is included to detect loss of PLL acquisition or a loss of input data. The MAX3270 has differential ECL input and output interfaces, so it is less susceptible to noise in a highfrequency environment. The fully integrated PLL includes an integrated phase-frequency detector that eliminates the need for external references.
____________________________Features
o Supports Both 155Mbps and 622Mbps Clock Recovery and Data Retiming o Fully Integrated Phase/Frequency Detector o Capable of Switching to an External Clock o Differential 100K ECL Data and Clock I/Os o Output Monitor Provides Lock Detection o No External Reference Clock Required
MAX3270
________________________Applications
155Mbps (STM-1/OC-3)/622Mbps (STM-4/ OC-12) SDH/SONET Transmission Systems 155Mbps/622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers Cross-Connects
______________Ordering Information
PART MAX3270EMH TEMP. RANGE -40C to +85C PIN-PACKAGE 44 MQFP
Pin Configuration appears at end of data sheet.
___________________________________________________Typical Operating Circuit
-2V +5V 11 VTTL 3 50 -2V 50 -2V +5V 4 41 42 13 18 20 14 SDIP 39 DVCC 17 19 DVCC DVCC 38 DVCC 7 AVCC 16 AVCC 15 AVCC 5 AVCC 24 OVCC 27 OVCC 29 OVCC 32 OVCC RDOP RDON RCOP RCON SDIN PHADJ VR EXCS CRS RST EXC 2 -2V EXCS AND CRS ARE CONNECTED FOR 622Mbps OPERATION. -4.5V -4.5V -4.5V ANALOG SUPPLY CRP 26 25 31 30 28 50 50 50 50 450 -4.5V
MAX3270
FILP FILG AVEE1 AVEE2 GVEE DVEE DVEE DVEE DVEE DVEE FILN FM 9 8 10 6 2.2F 20 2.2F 20
50
12
1
35
36 22 21 34 -4.5V DIGITAL SUPPLY
BYPASS SUPPLIES WITH 0.1F AND 0.01F CAPACITORS. DECOUPLE AVEE1, AVEE2, AND GVEE SUPPLY PINS.
________________________________________________________________ Maxim Integrated Products
1
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155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector MAX3270
ABSOLUTE MAXIMUM RATINGS
Supply Voltages VTTL to GND .....................................................-0.5V to +8.0V VCC to GND .......................................................-0.5V to +8.0V VEE to GND........................................................-8.0V to +0.5V SDIP, SDIN, EXC ...................................................-8.0V to +0.5V RDOP, RDON, RCOP, RCON, CRP.......................-8.0V to +0.5V EXCS, RST, CRS....................................................-0.5V to +8.0V FILP, FILG, FILN ....................................................-8.0V to +0.5V PHADJ, VR ............................................................-8.0V to +8.0V FM .........................................................................-8.0V to +8.0V Input Differential Voltage Level, SDIP, SDIN ......................+3.0V Continuous Power Dissipation (TA = +85C) .......................1.3W Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = -4.5V 5%, VTTL = 5V 5%, TA = -40C to +85C, unless otherwise noted.) PARAMETER Positive Voltage Supply (with respect to ground) Negative Voltage Supply (with respect to ground) Static Supply Current from VTTL Static Supply Current from VEE ECL INPUTS: EXC, SDIP, SDIN Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage LOW-POWER ECL OUTPUT: CRP Output High Voltage Output Low Voltage TTL INPUTS: CRS, RST, EXCS Input High Voltage Input Low Voltage Input High Current Input Low Current PHASE ADJUST INPUTS: PHADJ, VR Input Bias Current IBIAS VR = PHADJ = 0, TA = +25C 0 10 A VIH VIL IIH IIL VTTL = 5.00V, VIN = 2V VTTL = 5.00V, VIN = 0.8V 0 0 2 0.8 40 40 V V A A VOH VOL Loaded with 470 to VEE Loaded with 470 to VEE -1025 -1830 -955 -1705 -870 -1620 mV mV VIH VIL IIH IIL VOH VOL VIN = VOH (typ) VIN = VOL (typ) Loaded with 50 to -2V Loaded with 50 to -2V -1165 -1830 0 -100 -1025 -1830 -955 -1705 -870 -1475 100 100 -870 -1550 mV mV A nA mV mV SYMBOL VTTL VEE ITTL IVEE CONDITIONS MIN 4.75 -4.725 TYP 5.00 -4.50 2.4 150 MAX 5.25 -4.275 5 210 UNITS V V mA mA
ECL OUTPUTS: RCOP, RCON, RDOP, RDON
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155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector
AC ELECTRICAL CHARACTERISTICS (continued)
(VEE = -4.5V, VTTL = 5V, TA = 25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Loaded with 50 to -2V and 5pF to GND Loaded with 50 to -2V and 5pF to GND MIN TYP MAX UNITS
MAX3270
ECL OUTPUTS: RDOP, RDON, RCOP, RCON Transition Time 20% to 80% Time Difference between RDO and RCO tr, tf TD 600 100 ps ps
PFD AND FILTER AMPLIFIER TEST LEVELS Output Offset Voltage of the Monitor Amplifier Gain of the Monitor Amplifier Filter Amplifier Open-Loop Voltage Gain VCO TEST PARAMETERS; CPR OUTPUT Center Frequency Frequency Range Mean Frequency Sensitivity Frequency Sensitivity to Power-Supply Voltage PLL ELECTRICAL SPECIFICATIONS Frequency of VCO Incremental Tuning Sensitivity (Incremental Slope, f/Vt) Phase-Detector Gain Transconduction Gain of Filter Amplifier Phase Offset Sensitivity, /PHADJ FO DFO KO KOV FILP and FILN shorted, PFD = neutral state FILP - FILN = 1.6V FILP - FILN = 1.6V FILP and FILN shorted 38.00 6 3.75 39.50 10 6 550 MHz MHz MHz/V kHz/V VO GFM GOL PHADJ = 0, FILP and FILN shorted PHADJ = 0 FILP and FILN open -35 0.95 21 26 35 1.05 mV V/V dB
FO KO KD Gm KPHADJ ft = 622.08MHz
622.08 75 192 1.25 2
MHz MHz/V mV/rad mA/V rad/V
__________________________________________Typical Operating Characteristics
VEE SUPPLY CURRENT vs. TEMPERATURE
MAX3270-TOC9
CRP FREE-RUNNING FREQUENCY (VCO/16) vs. DIE TEMPERATURE
MAX3270-TOC5
190 185 VEE SUPPLY CURRENT (mA) 180 175 170 165 160 155 150 -40 -20 0 20 40 60 80 -4.25V -4.5V -4.75V
39.0 38.9 FREQUENCY (MHz) 38.8 38.7 38.6 38.5 38.4 38.3 MEASURED
100
0
10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
TEMPERATURE (C)
_______________________________________________________________________________________
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155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector MAX3270
__________________________________________Typical Operating Characteristics
JITTER TOLERANCE (155Mbps, 223-1 PRBS)
MAX3270-TOC1
10.0
AMPLITUDE (UI p-p)
1.0 DATA
0.1 10 100 1k FREQUENCY (Hz) 10k 100k
BELLCORE MASK 1M
JITTER TOLERANCE (622Mbps, 223-1 PRBS)
MAX3270-TOC2
10.0
AMPLITUDE (UI p-p)
1.0 DATA
BELLCORE MASK 0.1 10 100 1k FREQUENCY (Hz) 10k 100k 1M
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155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector
__________________________________________Typical Operating Characteristics
155Mbps RECOVERED CLOCK AND RETIMED DATA (SINGLE ENDED) 622Mbps RECOVERED CLOCK AND RETIMED DATA (SINGLE ENDED)
MAX3270
DATA
DATA
CLOCK
CLOCK
2ns/div
500ps/div
RECOVERED CLOCK JITTER (155Mbps, 27-1 PRBS, 5.1ps RMS)
RECOVERED CLOCK JITTER (155Mbps, 1-0 PATTERN, 4.7ps RMS)
RECOVERED CLOCK JITTER (622Mbps 27-1 PRBS 9.0ps RMS)
RF = 20 CF = 2.2F
RF = 20 CF = 2.2F
RF = 20 CF = 2.2F
10ps/div Mean 40.61ns RMS 5.13ps PkPk 45.6ps 1 2 3 68.961% 95.844% 99.717% Mean 40.65ns RMS 4.7ps PkPk 38.4ps
10ps/div 1 2 3 69.674% 95.558% 99.698% Mean 38.68ns RMS 9.049ps PkPk 79.4ps
10ps/div 1 2 3 69.747% 95.453% 99.582%
_______________________________________________________________________________________
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155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector MAX3270
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15, 16 17, 19, 38, 39 18 20 21, 22, 34, 35, 36 23, 33, 37, 40, 43, 44 24, 27, 29, 32 25 26 28 30 31 41 42 NAME GVEE AVEE1 SDIP SDIN AVCC FM AVCC FILG FILP FILN VTTL AVEE2 EXCS EXC AVCC DVCC CRS RST DVEE N.C. OVCC RDON RDOP CRP RCON RCOP PHADJ VR Negative Supply for Input Buffers: -4.5V Serial Data Input: 155Mbps or 622Mbps. Differential ECL Positive. Serial Data Input: 155Mbps or 622Mbps. Differential ECL Negative. Ground for Input Buffers: 0V Frequency Monitor Output. This pin monitors the input voltage to the VCO. When the PLL is locked, the pin will be 0V. Guard-Ring Positive Supply to Epi: 0V Loop Filter Ground. This pin connects to an external filter. Loop Filter Positive. This pin connects to an external filter. Loop Filter Negative. This pin connects to an external filter. TTL Positive Supply: +5.0V Negative Supply for VCO: -4.5V External Clock-Select TTL Input. A logical high selects the external clock. External Clock. Single-ended ECL input. Ground for VCO: 0V Digital Ground for Mux: 0V Clock-Rate Select TTL Input. This selects the clock rate to be either 155Mbps or 622Mbps. A logichigh level selects the 622Mbps mode. Resets all digital flip-flops, TTL input. Reset is assert when low. Digital Negative Supply: -4.5V No Connection Output Driver Ground: 0V Negative Recovered Data Output, differential ECL output: 155Mbps or 622Mbps. Positive Recovered Data Output, differential ECL output: 155Mbps or 622Mbps. Clock-Reference Output Divide-by-4. ECL low-power single-ended: 38Mbps or 155Mbps. Negative Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps. Positive Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps. Phase Adjust. This is an analog adjustment that varies the static phase between the input data and the recovered clock. If not used, this input should be grounded. The range is from -1V to 1V. Phase Reference Voltage: 0V. The PHADJ pin compares to this voltage. Set to ground. FUNCTION Guard-Ring Negative Supply to Substrate: -4.5V
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155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector
_______________Detailed Description
The block diagram of Figure 1 shows the MAX3270's architecture. The phase-locked loop (PLL) consists of a phase/frequency detector (PFD), a loop filter amplifier, and a voltage-controlled oscillator (VCO). bandwidth. The input data stream is sampled by quadrature components of the VCO clock, generating a difference frequency. Depending on the rotation of the difference frequency, the PFD will drive the VCO so that the difference frequency is driven to zero. Once frequency acquisition is obtained, the frequency detector will return to a neutral state.
MAX3270
Phase Detector
The phase detector produces a voltage proportional to the phase difference of the incoming data and the output of the recovered clock. Because of its feedback nature, the PLL will drive the error voltage to zero, making the phase difference zero and aligning the recovered clock to the incoming data. An external phase-adjustment pin (PHADJ) allows the user to vary phase alignment.
Loop Filter and VCO
The PLL is a second-order transfer function whose bandwidth is set by the loop filter. The VCO is integrated into the PLL and always operates at 622MHz. The center frequency is tightly controlled by laser trimming, limiting frequency drift when lock is lost. 155Mbps or 622Mbps mode is selected by the clock-rate select (CRS) pin. CRS selects the inputs to multiplexer MUX2. The internal VCO can be bypassed with an external clock applied to the EXC input. The external clock select (EXCS) controls the input selections to multiplexers MUX1 and MUX2.
Frequency Detector
A frequency detector is also incorporated into the PLL. Frequency detection aids in the acquisition of the input data; this frequency-aided acquisition is necessary during start-up conditions, since the input data stream and VCO difference frequency may be outside the PLL
PHADJ
VR
FILP
FILN FM 100k ECL D Q CLK 100k ECL CRP 38/155MHz 100k ECL RCOP RECOVERED CLOCK RCON EXCS
SDIP SDIN PHASE/FREQ DETECTOR CLK RST FILTER AMP VCO 622.08MHz
RDOP RECOVERED DATA RDON
DIVIDEBY-4
MUX 2 MUX 3 1 0 0 1
155MHz INPUT 622MHz
MUX 1
0
OUTPUT
1
EXC
MAX3270
RST CRS
Figure 1. Block Diagram
_______________________________________________________________________________________
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155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector MAX3270
__________________Design Procedure
Selecting the Data Rate
The MAX3270 is intended for use in SDH/SONET systems operating at 155.52Mbps or 622.08Mbps data rates. TTL inputs (CRS and EXCS) are provided for selecting the recovered clock rate (Table 1). It is also possible to switch to an externally supplied clock by enabling the EXC input. The EXC input is a high-speed single-ended ECL interface capable of handling serial clock rates of 155MHz and 622MHz.
MAX3270
Gm F(s)
FILP Rf
FILG Rf
FILN s Gm ( ___ + 1) wz F(s) = ____________ Cf s 1 wz = ____ Rf Cf Rf = 20 Cf = 2.2F
Table 1. MAX3270 Logic Table
EXCS 0 0 1 1 CRS 1 0 0 1 RCOP/RCON 155.52Mbps 622.08Mbps EXC EXC/4 CRP 38.88Mbps 155.52Mbps EXC/4 EXC/16
Cf Cf
Figure 2. Loop Filter
RECOVERED DATA OUTPUT (213-1 PRBS WITH 200 CONSECUTIVE ONES BER <10-12, 622Mbps)
Setting the Loop Filter
The loop filter within the PLL consist of a transconductance amplifier and the external filter elements Rf and Cf (Figure 2). The closed-loop bandwidth of a PLL can be approximated by: KD KO Gm Rf where KD is the gain of the phase detector, KO is the gain of the VCO, and Gm is the transconductance of the filter amplifier. Because this filter is an integrator, a zero in the open-loop gain is required for stability. This zero is set by the following equation: wz = 1 / (Rf Cf) where the recommended external values are Rf = 20 and Cf = 2.2F. To decrease the PLL's closed-loop bandwidth, reduce the value of Rf. Decreasing this bandwidth will improve the MAX3270's jitter transfer performance but reduce jitter tolerance. The MAX3270 has been designed (using the recommended values of Rf and Cf) to meet the Bellcore and CCITT specifications for jitter tolerance of a Network Element. Carefully consider the application if a reduction in loop bandwidth is desired. By reducing Rf an order of magnitude, the PLL's bandwidth becomes more sensitive to the internal tolerances of the IC. As a result, the loop bandwidth may have a wider variation. If Rf is reduced, then Cf should also be increased to maintain loop stability and minimize jitter peaking.
200 ONES
PRBS
1.532s
100ns/div
2.532s
Figure 3. Recovered Data Output
The MAX3270 is optimally designed to acquire lock and to provide a bit-error rate (BER) of less than 10-12 for long strings of consecutive zeros or ones. Using the recommended external values for Rf = 20 and Cf = 2.2F, measured results show that the MAX3270 can tolerate more than 200 consecutive ones or zeros. Figure 3 shows a bit stream of 213 - 1 PRBS with 200 consecutive ones.
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_______________________________________________________________________________________
155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector
Input and Output Termination
The MAX3270 data and clock I/Os (SDIP, SDIN, RDOP, RDON, RCOP, RCON, and EXC) are open emitters, designed to interface with ECL signal levels. It is important to bias these ports appropriately. A circuit that provides a Thevenin equivalent of 50 to -2V should be used with fixed-impedance transmission lines for proper termination. Figure 4 shows some typical input and output termination methods. The serial data input signals (SDIP and SDIN) are the differential inputs to an emitter coupled pair. As a result, the MAX3270 can accept differential input signal levels as low as 250mV. The serial input (SDIP) can also be driven single-ended by externally biasing SDIN to the center of the voltage swing (approximately -1.3V). Make sure that the differential inputs and outputs each see the same termination impedance for balanced operation. CRP is also an open-emitter ECL output, but it requires a termination resistor of 450 to -4.5V. If this output is not used, reduce power by connecting CRP to V EE through a resistor valued at 10k or more. The MAX3270's performance can be greatly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductances and using fixed-impedance transmission lines on the data and clock signals. Powersupply decoupling should be placed as close to the VEE and VTTL pins as possible. AVEE1, AVEE2 and GVEE should each have their own bypass/decoupling elements, independent of each other and any other 4.5V supply. Make sure to isolate the inputs from the outputs to reduce feedthrough.
MAX3270
__________Applications Information
Lock Detection
The MAX3270 has an output (FM) that monitors the input voltage to the VCO. FM is an analog output that can be used as a flag to indicate that the PLL is locked. Under normal operation, the loop is locked and the FM output is approximately equal to 0V. When the PLL is unlocked, the VCO will drift. The FM output monitors this drift and will equal approximately 1V in the limit.
Phase Adjust
In some applications, the optimum alignment point between the recovered clock and the serial data is not at the center of the eye diagram. The MAX3270 has a PHADJ input that can be used in these applications to introduce a phase difference between the recovered clock and the serial data. When no phase difference is desired, this input should be set to 0V. The VR pin is the reference input for PHADJ and is normally tied to GND.
Zo = 50 Zo = 50
ECL INPUTS ECL OUTPUTS
Zo = 50 Zo = 50
90.9 Zo = 50 50 50 -2V Zo = 50 111
90.9
MAX3270
ECL INPUTS ECL OUTPUTS
90.9 Zo = 50 Zo = 50
90.9
MAX3270
50 -2V CRP 50
-4.5V 450 -4.5V
111 CRP 450 -4.5V
111
111
-4.5V
50 to -2V TERMINATION
THEVENIN EQUIVALENT TERMINATION
Figure 4. Typical Input and Output Terminations
_______________________________________________________________________________________
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155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector MAX3270
__________________Pin Configuration
TOP VIEW
N.C. N.C. VR PHADJ N.C. DVCC DVCC N.C. DVEE DVEE DVEE 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
GVEE AVEE1 SDIP SDIN AVCC FM AVCC FILG FILP FILN VTTL
1 2 3 4 5 6 7 8 9 10 11
MAX3270
N.C. OVCC RCOP RCON OVCC CRP OVCC RDOP RDON OVCC N.C.
10
______________________________________________________________________________________
AVEE2 EXCS EXC AVCC AVCC DVCC CRS DVCC RST DVEE DVEE
12 13 14 15 16 17 18 19 20 21 22
MQFP
155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector
________________________________________________________Package Information
DIM MILLIMETERS MIN MAX 2.032 2.388 0.102 0.254 1.930 2.134 0.305 0.457 0.102 0.254 12.954 13.462 9.906 10.109 3.429 REF 12.954 13.462 9.906 10.109 3.429 REF 0.800 REF 0.660 0.940 0 10 INCHES MIN MAX 0.080 0.094 0.004 0.010 0.076 0.084 0.012 0.018 0.004 0.010 0.510 0.530 0.390 0.398 0.315 REF 0.510 0.530 0.390 0.398 0.315 REF 0.315 REF 0.025 0.037 0 10
21-0826A
MAX3270
SEE DETAIL "A" C
DETAIL "A"
A2 L A1
A
D D1 D3
E E1 E3
A A1 A2 b C D D1 D3 E E1 E3 e L
44-PIN MQFP METRIC QUAD FLAT PACK
b e
______________________________________________________________________________________
11
155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector MAX3270
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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